Sr System Design Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The HBM DTPCO (Design, Technology, Packaging Co-Optimization) Characterization Engineer is a highly technical, hands-on role focused on deep characterization of HBM cubes across thermal, mechanical, and electrical domains, and on driving power, performance, area, cost, and time-to-market improvements. 

The core mission of this position is to fundamentally understand HBM cube behavior and failure modes through meticulous bench testing, structured experimentation, and data-driven analysis. The engineer will generate high-quality characterization data, connect observations across domains, and translate insights into actionable structural, technical, packaging, test, and product solutions.  
This role is key to achieving DTPCO objectives by building a first-principles understanding of the HBM cube's limitations. It involves validating hypotheses with silicon data and supporting modeling, yield improvement, and adaptability of next-generation HBM products. The role plans and performs custom bench-level HBM cube tests involving temperature, mechanical stress, and electrical elements. Tests cover steady-state and transient thermal effects, power/thermal correlation, warpage, stress behavior, IDD, timing margins, parametrics, and fail signatures.

Responsibilities:

• Compose, build, and debug custom bench setups, fixtures, and measurement flows using lab equipment such as power supplies, SMUs, oscilloscopes, thermal hardware, handlers, sockets, and probe cards.

• Perform full thermal and mechanical stress characterization using bench stress platforms (e.g., Arora‑type testers) while monitoring electrical behavior under controlled stress.

• Conduct hot/cold, transient, and forced‑temperature testing with precision thermal systems (e.g., Sensata‑type chillers or thermal forcing units) to enable power–temperature correlation and failure‑onset analysis.

• Develop Python‑, Verilog‑, and C/C++‑based test programs to build targeted stress patterns, segmented workloads, custom modes, and observability hooks that accelerate root‑cause isolation.

• Drive correlation of bench results with assembly, test, and system-level data, including DOE-based studies to isolate sensitivities and interactions across thermal, mechanical, electrical, and structural domains.

• Analyze MBIST signatures and electrical or thermal behavior. Trace issues back to building, technology, package, or assembly root causes. Collaborate with test teams on improved screens and content.

• Lead failure‑mode identification and statistical analysis of multifaceted datasets to deliver clear, evidence-backed recommendations for building, process, package, or test mitigations while partnering closely with HBM Build, DTPCO, Technology Development, Packaging, Test, Product Engineering, and Reliability teams.

Minimum Qualifications 

• A BS or equivalent experience with 8 years of proven experience is also acceptable. A Master’s degree or equivalent experience in electrical engineering, computer engineering, mechanical engineering, materials science, or a related field is required.

• Strong fundamentals in semiconductor devices, memory architectures, and manufacturing/process flow. 

• Hands-on experience with silicon or package-level characterization, bench/ATE testing, or product/test engineering. 

• Confirmed understanding of electrical measurement techniques, lab instrumentation, and test platforms. 

• Experience with programming and data analysis (Python, JMP/JSL, C/C++, or similar). 

• Proven understanding of statistics and experimental methods (DOE). 

• Ability to independently debug sophisticated problems and synthesize conclusions from incomplete or noisy data. 

Preferred Qualifications 

• Direct experience with HBM, DRAM, or advanced memory products. 

• Experience running or analyzing MBIST-based testing and correlating to silicon behavior. 

• Background in package product engineering, test solutions engineering, or silicon characterization. 

• Familiarity with thermal and mechanical modeling concepts and correlation to lab data. 

• Experience working across design, technology, package, and test teams to close issues. 

• Demonstrated ability to turn characterization da