Staff Engineer, ASIC Validation

CA Pay Range (Annual):

$134,400.00 - $249,600.00

Non-CA Pay Range (Annual):

$121,000.00 - $224,600.00

At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on the terms of the Company’s incentive plans, the Company’s financial performance, and/or individual employee job performance.

Infinera also offers paid leave, medical, 

dental, and vision coverage, 401(k),

life, and disability insurance to

eligible employees.

Infinera is the global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs. We design, develop and deliver hardware and software for fiber-based connectivity solutions that span access, aggregation, metro, long haul, and submarine network. Our industry-leading, trendsetting edge-to-core solutions provide the foundation for many of the world’s largest and most demanding networks that generate billions in service revenue for our customers.

Your Key Responsibilities Would Include:

In this role, you will have complete ownership of specific tasks – validation env development and/or validation & characterization of specified functional features. You will work under the guidance of a person managing overall ASIC/FPGA validation, and you will have ownership of a subset of tasks. You will have full ownership of technical quality and timely completion of a project.

What you will be doing:

• Participate in the specification of validation env & component selection required to carry out validation
• Work on validation env if required
• Define & own validation plan for a subset of features
• Participate in system-level debug to isolate issues related to ASIC/FPGA
• Participate in full chip validation & characterization efforts
• Participate in process & checklist definition & improvements
• Mentor team members

Education & Experience Necessary For Success:

• Experience: 6+ yrs with MS & 8+ yrs with BS, of which 3-4 yrs of Mgmt experience
• Experience with post-silicon validation
• Experience with scripting languages, preferably Python
• Basic RTL design & verification skills & proficiency in DSP logic validation and DSP design constructs
• Should be able to review the arch, requirements and micro-arch details
• Good communication and interpersonal skills.
• Ability to contribute towards improving validation methodology
• Explore new methodologies to improve quality and reduce pain points in the project execution

#LI-SR2

“This position requires direct or indirect access to certain confidential information, hardware, software, technology, or technical information (referred to here as “Export-Controlled Information”) controlled under the U.S. International Traffic in Arms Regulations (ITAR) and/or the U.S. Export Administration Regulations (EAR). All personnel in this position must be eligible to or be able to obtain authorization from the appropriate agency to access applicable Export-Controlled Information. The U.S. Department of Commerce currently requires a foreign person with a most recent citizenship or permanent residency of Sudan, Ukraine, or a country currently designated in Country Group D:1, E:1 or E:2 (Supplement No. 1 to Part 740, Title 15) to have an export control license to access our Export-Controlled Information, unless they meet certain exemptions provided under U.S. export control laws and regulations. The list of applicable countries in Country