Job Details:

Job Description: 

Performs functional verification of CPU logic to ensure design will meet specification requirements.

Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to CPU microarchitecture specifications.

Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.

Replicates, root causes, and debugs issues in the presilicon environment.

Finds and implements corrective measures to resolve failing tests.

Collaborates with CPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.

Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.

Maintains and improves existing functional verification infrastructure and methodology.

Participates in the definition of architecture and microarchitecture features of the CPU being designed actively.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications

The candidate must have a Bachelor's degree in Electrical/Computer Engineering, Computer Science or other Science/Engineering related field and 6+ years of experience or Master's degree in Electrical/Computer Engineering, Computer Science or other Science/Engineering related field and 4+ years of experience.

Minimum of 4+ years experience in pre-silicon verification and/or front end. Minimum of 2+ years experience with software/programming languages (i.e. C, C++, C#, Visual Basic/.NET. Perl, Python, Java, etc.)

Minimum of 2 years experience with System Verilog/Verilog/VHDL, Verification, Validation and/or VCS or similar Simulator.
Minimum of 6 months experience with computer architecture and microarchitecture

Preferred Qualifications:
Experience with coverage driven validation

Experience in IP/SOC ASIC Validation

Experience in Specman E and/or System Verilog/OVM/UVM

Experience with software design and coding

Familiarity with x86 core architecture and instruction set is a plus

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Folsom

Additional Locations:

Business group:

The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core ™, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:  https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$123,419.00-$185,123.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybri