HBM Memory Subsystem Architect – MTS/SMTS/DMTS

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Description

Join an inclusive team passionate about one thing: using their expertise in the steadfast pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

You will be responsible for the design & development of next generation HBM DRAM products. You will join a multi-functional group of technical experts working closely with customers, partners, and a distributed team from Build Engineering, Product Engineering, Process Development, Package Engineering, and Business Units. Together, you will complete tasks aimed at ensuring the success of our future HBM roadmap.

The HBM Design Architecture group is looking for an experienced Memory Subsystem Architect to work with internal and external partners to investigate, define, and develop innovative new memory subsystem architectures building on our Industry leading HBM product solutions. The AI/ML transformation underway demands breakthrough memory and computing solutions. We believe our HBM product roadmap is foundational in enabling these new exciting solutions. The HBM Design Architecture group collaborates closely with Industry partners to investigate and develop products aligned with customer needs and technology trends extending over 3-5 year timeframe.

Responsibilities

• Develop innovative memory subsystem frameworks for HBM solutions supporting AI/ML workloads, including PHY, controllers, NOC, microcontrollers, MBIST, interfaces, and adapters.
• Define Memory and RAS architecture requirements and drive architectural planning for next‑generation memory subsystems.
• Collaborate with internal and external partners to develop novel architectures and detailed IP requirements.
• Lead engagement with IP vendors, including evaluation and selection of interface and functional IP.
• Analyze benchmarks, workloads, and simulations to identify opportunities for performance, efficiency, and architectural innovation.
• Model performance, performance/watt, gate count, power, and area; create architectural and external‑facing specifications aligned with protocol and hardware standards.
• Partner with RTL, validation, and product teams to ensure timely and successful implementation, participating in design reviews for HBM and memory subsystem features.
• Drive microarchitecture definition, participate in performance simulation and benchmarking, and debug issues across models, RTL, and IP.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 15 years of experience in memory subsystem architecture and design.
• Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM).
• Experience with PHY design and understanding of signal integrity issues.
• Proficiency in Network-on-Chip (NoC) architecture and design.
• Familiarity with industry-standard bus protocols such as AXI, AMBA, AHB, DFI, etc.
• Strong analytical and problem-solving skills
• Excellent written and verbal communication skills

Preferred Qualifications

• PhD or equivalent experience in a relevant field
• Familiarity with EDA tools for design and verification
• Practical experience with multi-core systems, coherent interconnects & Industry IO protocol like PCIe/CXL, confidential compute, virtualization & security
• Knowledge of serial link protocols (UCIe etc.) is desired

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$177,000.00 - $387,000.00 a year

Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your pref