Digital Verification Engineer, Sr. Staff

General Information

Job Title Digital Verification Engineer, Sr. Staff Job ID 4882 Country Italy City Pavia Date Posted 03-Sep-2024 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No

Descriptions & Requirements

Job Description and Requirements Synopsys is seeking for a highly motivated and innovative digital verification engineer with exceptional knowledge in the verification of high-speed digital designs. The candidate would be working as part of a highly experienced mixed-signal design and verification team and will be involved in verifying current and next generation PAM-based SerDes products. The position offers an excellent opportunity to work with a skilled team of digital and mixed-signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips.

Main Responsibilities:

• Writing modular constrained-random Verilog and System Verilog testbenches 
• Performing functional coverage 
• Assertion coverage and code coverage 
• Creating and tracking test-plans 
• Evaluating failure cases and running gate-level simulations 

Key Qualifications:

• BSEE or MSEE with 10+ years of digital verification experience in the industry 
• Must have hands-on experience in writing complex testcases in Verilog and SystemVerilog 
• Must have familiarity with cod