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Avionics FPGA Design and Verification Chief Principal Engineer

Boeing
United Statesfull_timeVerifiedPosted 13 Jan 2025
💰 $257,600/yr($177,650/yr$257,600/yr)

About the role

Avionics FPGA Design and Verification Chief Principal Engineer

Company:

The Boeing Company

Job ID:

00000440481

Date Posted:

2025-01-13

Location:

USA - Hazelwood, MO, USA - Mesa, AZ, USA - Plano, TX

Job Description Qualifications:

Boeing is currently looking for an Avionics FPGA Design and Verification Chief Engineer at the Principal level to join our team in Hazelwood MO, Plano TX, or Mesa, AZ.

The successful candidate will be responsible for leading the technical development of a distributed group of engineers focused on FPGA Design, Verification, and Certification for Boeing AvionX products.

This position involves technical leadership for a team that develops FPGA solutions for Vehicle Management Systems (VMS), Guidance and Control Units, Computing and Network Infrastructure, and Electrical Power Systems products.  These products are used in many Boeing products such as F-15 Fighter, T-7A Trainer, MQ-25 Autonomous Refueler, Weapons Programs, Commercial Aircraft, and many more.

Position Responsibilities:

  • Lead FPGA designs, including multi-FPGA programs and teams with design and verification engineers, and manage team execution to meet program milestones

  • Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs

  • Explore trade-space of potential FPGA technologies and determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance

  • Implement FPGA with latest design practices and tools from block-level microarchitecture and through HDL coding

  • Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensurethe design is completed on schedule

  • Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation

  • Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to create drivers, monitors, predictors, and scoreboards

  • Drive FPGA-based prototyping and validation depending on program and system requirements and complexity

  • Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed

  • Train and mentor less senior engineers across the department and help build effective project teams

This position is expected to be 100% onsite.  The selected candidate will be required to work onsite at one of the listed location options.
 

This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret clearance post-Start is required.

Basic Qualifications (Required Skills/Experience):

  • Bachelor of Science degree from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), chemistry, physics, mathematics, data science, or computer science

  • 10 or more years of professional experience with Hardware-based integration and test of ASIC/FPGA designs

  • 10 or more years of educational and/or work experience working with digital ASIC/FPGA design and verification

Preferred Qualifications (Desired Skills/Experience):

  • Experience with hardware emulators

  • Experience leading FPGA design and/or verification teams, including tracking and reporting progress to stakeholders

  • Leading FPGA design and/or verification teams, including tracking and reporting progress to stakeholders

  • Proficiency with hardware verification languages: System Verilog, System Verilog Assertions

  • Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.

  • Ability to create test plans and self-checking and reusable testbenches from scratch

  • Experience developing Functional Coverage Models and Closing Code Coverage

  • Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)

  • Proficient in scripting languages: Make, Perl, Python, etc.

  • Revision Control Systems: svn, cvs, git

  • Proficient in Linux Environments

  • Familiarity with

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Company

Boeing

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