Senior DDR IP Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

 We are looking for a DDR IP DV Individual Contributor Engineer to join the team.

#SCHIE #CSME

Position responsibilities will include:

• Own or lead verification of one or more aspects/features of a memory controller Intellectual Property (IP) and/or Double Data Rate (DDR) subsystem integration with Physical Layer (PHY) 
• Learn about the design and interact with partner teams to define verification strategies and test plans
• Develop verification environments and run and debug simulations to drive quality
• Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
• Innovate to improve verification efficiency through methodologies or tools
• Apply industry leading generative AI solutions to verification work
• Coach and mentor others in your areas of expertise
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Required Qualifications:

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Preferred Qualifications:

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ year(s) technical engineering experience or internship experience.
  • OR Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field.
• 5+ years of pre-silicon subsystem or IP verification experience.
• 3+ years of DDR subsystem verification experience.

• Demonstrated experience in verifying memory controller, DDR PHY, and/or at DDR sub-system level including integration verification of memory controller IP with DDR PHY and Electronic Design Automation (EDA) vendor sourced Dual In-line Memory Module (DIMM) Verification IP (VIP)
• Deep understanding of JEDEC spec including mode registers, tim