Sr Design Verification Engineer

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet.

 

Job Summary

We are seeking an experienced Engineer to bridge the gap between design teams, technology development, and manufacturing reality. In this role, you will act as the ultimate quality gatekeeper. You will define, validate, and enforce physical layout rules (DRC/LVS) and automation software code used across multiple engineering groups. Your work will directly ensure first-time-right layouts and optimal yield by auditing deliverables from internal teams and external vendors. You will support the implementation of new technologies that are under development and continuous improvement of existing technologies for Qorvo, Inc.

Key Responsibilities:

Layout & Physical Verification

• Enforce sign-off compliance across all design groups using physical verification tools.
• Evaluate and test Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Process Development Kit (PDK) decks as well as mask automation code and other internal coding systems.
• Review complex layout fixes with design and technology teams to resolve issues.
• Collaborate with other teams to interpret and implement advanced process design kit (PDK) layout rules.

Software, Automation & Methodology

• Audit and validate internal software scripts, code infrastructure, and automation workflows.
• Build automated regression tests to ensure multi-group deliverables do not break the overall tape-out flow.
• Develop Golden Standards for new and existing technologies to ensure quality of code.
• Create unified design methodologies to standardize how different teams write code and handle layouts.
• Provide technical support and tool training to logic design, physical design, and layout teams.

Required Qualifications:

Education & Experience

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or related field
• 5+ years of experience in semiconductor physical verification, CAD, or design automation. Experience in compound semiconductors such as GaN, GaAs, pHEMT, transistors is a plus.

Technical Skill Set

• Industry Standard Tools: Deep hands-on experience with Siemens Calibre (DRC/LVS), Synopsys IC Validator, or Cadence Pegasus.
• Scripting & Software: Advanced proficiency in scripting to automate verification flows.
• Semiconductor fabrication knowledge: Familiarity with semiconductor processes and technology development methodologies.
• Rule Writing: Proven ability to read, write, and debug runsets and verification rule decks.

Preferred Qualifications

• Experience auditing cross-functional teams or managing multi-site tape-out flows.
• Familiarity with revision control systems
• Strong communication skills to negotiate layout trade-offs and code quality standards with diverse engineering teams. 

 

This position is not eligible for visa sponsorship by the company

 

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