Sr. RTL Engineer

About us: 

With offices in the U.S. and Germany, MicroVision is at the forefront of driving the global adoption of innovative perception solutions, with the goal of making mobility and autonomy safer. Our engineering excellence, based in Florida, Washington State, Washington D.C., and Hamburg, Germany, enables us to develop and supply integrated lidar hardware and perception software solutions. Our proprietary technologies enhance safety and automation across various industrial applications, including robotics, automated warehouses, and agriculture, and are instrumental in the development of autonomous systems. MicroVision’s core technology, initially developed for the automotive industry, continues to accelerate advanced driver-assistance systems (ADAS) and autonomous driving. Building on our history of providing technology to the military segment, our target offerings include semi- and fully autonomous airborne and terrestrial sensor systems. With our solid-state lidar technologies, encompassing MEMS-based long-range lidar and flash-based short-range lidar, integrated with our onboard perception software, MicroVision possesses the expertise to deliver safe mobility at the speed of life.   

Job Summary:  

MicroVision has an immediate opportunity for a Senior RTL Engineer.  As a key member of MicroVision's growing Digital Design Engineering team, you will collaborate with various technical teams in the company to design and take into production, market defining Automotive LiDAR product. The right candidate for this position will be a highly motivated FPGA/RTL Engineer with a breadth of understanding in FPGA design and best practices, including detailed design, System Verilog coding, modelling, simulation, verification, integration and test. 

Essential Duties and Responsibilities:  

• Derive FPGA requirements based on system requirements then create FPGA architecture to fulfill those requirements 

• Design, implement and test Register-Transfer Level (RTL) features and components guided by system architecture and requirements 

• Own the detailed design of assigned firmware components and subsystem functionality 

• Document test and implementation plans at unit at system levels and then execute on it. 

• Work with other teams to integrate developed features into system hardware. 

• Support bringing up RTL features developed by the team. 

• Coach/mentor junior members of RTL and integration teams to complete tasks. 

• Participate in the full software development life cycle (SDLC) flow including peer reviews of requirements, architecture, design, and code implementations within an approved ASPICE development flow. 

Required Knowledge, Skills and Abilities:  

• Knowledge of System Verilog, Verilog, Python programming languages 

• Proficient in FPGA Design methodologies from state machine design to DSP implementation 

• Experienced in closing timing in FPGA designs. 

• Mapping algorithms to FPGA appropriate logic implementations 

• Expert integrating and bringing up features in hardware. 

• Ability to work well in a fast-moving and complex environment.