Embedded HPC Engineer (Real-Time Edge Compute)

Company Overview

Metrea delivers effects-as-a-service to national security partners across five domains and more than a dozen mission areas—including airborne ISR, electronic warfare, secure communications, aerial refueling, special mission aviation, aerial firefighting, and advanced simulation. 

Wherever we operate, we build vertically integrated full stacks of capability—designing, building, and operating turnkey solutions that let customers scale capacity while benefiting from continuous cycles of innovation. With operators and engineers under one roof, we close the gap between lab and field—what we call connecting design with effect. 

Metrea’s solutions are built for elegance: effective, efficient, and evolving. This approach enables our partners to do more with less and achieve outsized, asymmetric advantage against rapidly evolving threats. 

Headquartered in Washington, DC, Metrea has facilities across the United States, the United Kingdom, Europe, and beyond.

Group Overview: 

Electromagnetic and Cyber Group (EM&C) is responsible for developing flexible and survivable advanced electronic warfare and secure communications equipment while providing the industry’s leading signals intelligence, electronic warfare, and cyber experts. Metrea specializes in signal classification, direction finding, advanced geolocation techniques, and waveform development including waveforms for MANET and LPI/LPD applications. Metrea also develops special purpose radios for government customers and licenses DF and geolocation solutions to multiple OEMs.

Position Summary 

The Embedded HPC Engineer (Engineer II) develops and integrates embedded software components that mature RADLAB radar R&D algorithms into a robust, testable, real-time processing system on edge CPU/GPU platforms. This role focuses on implementing high-rate sensor ingest pipelines, building record/replay and validation infrastructure, integrating SDR and compute platforms, and optimizing performance to meet defined latency, throughput, and determinism targets under guidance from senior technical leadership.

Role and Responsibilities 

• Implement real-time software components that operationalize RADLAB radar algorithms, including dataflow stages, buffer management, error handling, and state management.
• Support SDR and compute-platform bring-up by executing baseline boot/configuration procedures, integrating drivers and device APIs, enabling streaming modes, and performing stability/soak testing under sustained high-rate load; escalate and document integration issues with clear repro steps.
• Develop and maintain high‑throughput data pipelines from ingest through embedded compute and into high‑speed storage, including buffering strategies, backpressure control, integrity verification, and record/replay workflows.
• Contribute to deterministic behavior by implementing concurrency, prioritization, and bounded-latency patterns (e.g., lock avoidance, bounded queues, careful memory ownership) to meet predefined timing budgets and jitter targets; measure and report timing performance.
• Integrate standard interfaces across the stack such as device control APIs, networking/high-speed I/O, storage, time sync, and telemetry.
• Validate algorithm implementation fidelity by integrating reference implementations, running golden vectors/recorded datasets, computing defined equivalence metrics/tolerances, and investigating mismatches with disciplined root-cause analysis.
• Perform performance profiling and optimization of assigned subsystems using established tools and methods (e.g., CPU affinity guidance, memory reuse, reduced copies, cache-aware data layouts, pipeline parallelism); propose and prototype improvements with evidence.
• Build and execute acceptance and regression tests using golden vectors and recorded datasets; produce concise validation notes with pass/fail criteria, performance measurements, and issue triage outcomes.
• Develop and maintain test rigs, bench procedures, and automation for repeatable bring-up and regression testing; contribute to CI/CD for hardware-coupled system, including build artifacts, smoke tests, on-target hooks.
• Provide engineering feedback on constraints discovered during implementation, such as throughput, latency, memory, quantization, real-time feasibility, to R&D (Algorithm) Engineers, Hardware Engineers, and the Head of RADLAB, and implement mitigation