Principal Engineer, DFT (Design for Testability)

Microsoft's hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, business, and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Our opportunities represent a variety of disciplines including, but not limited to, design, verification, performance modeling, and DevOps supporting the development of custom silicon. Microsoft’s hardware teams are also expanding into new technologies such as quantum computing! We are looking for the best and brightest to join us in designing for the future! 

As a Principal Engineer, DFT (Design for Testability) in the Silicon Engineering and Solutions team, you will drive DFT solutions for the product and be at the center of chip design and enabling effort all the way from defining architecture, helping with implementation, ensuring verification coverage and finally with silicon bring-up and validation, for our projects. This will involve numerous projects within Microsoft developing custom silicon for a diverse set of systems.  We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. 

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.  

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day. 

Responsibilities

• Design and develop scan insertion and memory BIST (built in self test) insertion, and test the silicon, debug and validate the DFT (design for testability) features on the ATE (automatic test equipment).
• Improve the design, development, and overall quality of the hardware products and development processes. 
• Work on memory BIST design optimization to make sure design is time, power, and area efficient.  Collaborate on a regular basis with memory unit owners for DFT architecture and flow development.
• Develop methodology and flows for verification and debugging as well as anticipate and avoid blocking issues on projects.  Develop ATE test patterns and algorithms to cover various memory and scan fault models.  Work on infrastructure and test flow development for unit level and full chip verification.
• Proactively identify new tools, technologies, and methods to do the job, and understand customer issues for DFT and BIST insertion.  Analyze and compare different tools and methods and compare parameters such as area overhead, timing to optimize the DFT solution for the project.
• Evaluate cost of DFT in terms of die are and test time, cost of memory diagnostics, and benefit of yield recovery for logic and memory redundancy. 
• Justify and show return on investment (ROI) for BIST and logic redundancy. 
• Measure repair rates of each chip and identify outlier memory designs that perhaps need circuit work or manufacturing improvement.

Other

• Embody our Culture and Values

Qualifications

Required/Minimum Qualifications

• 9+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 9+ years demonstrated experience in DFT (design for testability) for VLSI (very large scale integration) design.
• 9+ in scan insertion, ATPG (automatic test pattern generation), MBIST (memory built in self-test), JTAG (joint test action group), IO (input/output) BIST, Scan Compression, and at-speed testing

Other Qualifications

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cl