Principal HBM Physical Design Architect

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our Opportunity Summary:

For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

As an HBM Physical Design Architect, you will be responsible for the design & development of next-generation HBM DRAM products. You will be part of a highly multi-functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to execute the implementation goal of ensuring our future HBM roadmap is successful. You will apply your deep understanding of memory array architectures, high-speed interface design, logic & custom circuit design, memory subsystem operation, high-performance computing architectures, and 2.5D & 3D package integration to understand and analyze bottlenecks and propose innovative architectures to target outstanding performance, power, cost, reliability and quality for Micron’s HBM product portfolio. 

(Disclaimer): While you may not exhibit all of the characteristics/skills listed below today, we are highly interested in a teammate who is motivated to grow in technical breadth and depth. Suppose you are open to learning while being a valued member of a team of premier engineers. In that case, we are determined to help build upon your existing foundation, while rapidly growing your individual and collaborative skills in this exciting and outstanding opportunity.

*This position will be a hybrid role located in either Folsom, CA, Allen, TX, or Atlanta, GA.

*The seniority level offered will be based on a combination of experience and education.

What’s Encouraged Daily:

• Defining effective design partitioning and circuit architecture to convert fully custom and asynchronous designs to fully synthesizable and synchronous designs.

• Working with external customers and IP vendors as well as internal design teams to integrate IP blocks into a fully functioning design.

• Evaluating and driving optimization of power, performance, and area of key design blocks across various process nodes.

• Pathfinding to explore new architectures for future HBM products and make recommendations after performing a highly technical feasibility analysis.

• Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products and architectures.

• Engage with Customers to support issues with current HBM architectures and find opportunities to innovate on future HBM solutions.

• Focus areas within the team will include memory array architectures, on-die and off-die high-speed signaling, PHY & interface development, power delivery network planning and optimization, power consumption reduction, CMOS requirements identification, packaging technologies, and thermal modeling.

How To Qualify:

• Experience and expertise across the various areas of physical design, including timing closure and STA, clock tree synthesis, floor planning, and power/performance/area optimization.

• Experience with industry-standard physical design tools and working in a foundry design environment.

• Familiarity with DRAM operation and JEDEC specifications, preferably with the HBM product family.

What Sets You Apart:

• In-depth technical expertise in one or more areas - DRAM memory array design, high-speed clocking and interface development, logic and custom circuit design, power delivery optimization, CMOS & semiconductor device physics, 2.5D and 3D packaging technologies

• Good verbal and written communication skills with the ability to effectively synthesize and convey complex technical concepts to other partners and leadership

• Strong track record of innovation and problem-solving in high-performance memory development

• Bonus - Good understanding of Memory subsystem operation in high-performance computing applications

• Prior experience with DRAM product bring-up and debug

• Prior experience with package technologies (TSV, hybrid bonding, interposers, etc)

• BSEE or greater