Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design

Microsoft Quantum has assembled a talented and diverse international team to create the world’s first scalable quantum computing system. Our full-stack approach involves exciting innovations from physics on the quantum plane to providing global quantum services. The Microsoft Quantum program strives to fundamentally change the world of computing to help solve humankind’s currently unsolvable problems. We are on the cusp of an accelerated effort in quantum computing.

This position offers an opportunity to have a meaningful influence on a revolutionary technology. The research effort includes a diverse staff of theoretical and experimental physicists, hardware designers and software engineers around the world. We are looking for a Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design. Our Cryo-CMOS team is looking for an experienced application-specific integrated circuit (ASIC) designer to participate in the research and development of essential building blocks in the control and readout chain of our quantum hardware implementations. 

Microsoft's mission is to empower every person and every organization on the planet to achieve more. At Microsoft Quantum, we aim to empower science and scientists to solve the world's biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence, and quantum information technology. 

Responsibilities

This role involves deep, technical work in a small, collaborative environment. We are looking for someone who is as passionate about their own contribution as they are to empowering and inspiring others. The candidate will be responsible for contributing to the technical direction of the research based on system and block design ideas and simulations, experimental results, program needs and the input from cross-functional colleagues.  

Key Responsibilities include:  

• Contribute to the architecture, specification, design, test, and development of CryoCMOS functions and ASICs to support the full-stack quantum hardware implementations. 
• Be responsible for  
  • Logic design/Register Transfer Level (RTL) entry  
  • RTL to GDS implementation in Physical Design domain, from synthesis to place and route of partitions through all signoffs including timing signoff, physical verification, EMIR signoff, and Low Power Verification. 
  • Define and implement efficient UVM-based verification environments and use them to verify+test digital designs 
  • Test plan, tests and infrastructure to complete formal validation of complex design and report bug/issues 
  • Effective team collaborator that will work closely with the analog, architecture, and cryogenics teams to optimize tradeoffs within the design. 

• Conduct cryogenic and room temperature measurements of the ASICs and perform analysis and reporting of the measurement results. 

• Use lab best practices and protocols. 

• Work in accordance with health and safety policies and take care that your actions do not impact on the health and safety of yourself or others. 

• Ensure hazards and risks are identified and controlled for within your area of responsibility. 

Other:

• Embody our Culture and Values

Qualifications

Required/minimum qualificati