Senior Principal Switch Architect

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

You will join the high-performance Teralynx Switch Architecture Team, the group responsible for defining the architecture of Marvell’s next-generation data center switch ASICs. This team owns:
• Product architecture definition
• Behavioral modeling
• Performance modeling & analysis
• Architecture validation
• Feature & protocol definition
• Cross-functional technical leadership
You will collaborate directly with ASIC design, SerDes, firmware, validation, systems engineering, and product teams to bring new switch architectures from concept to silicon and production.

Why Marvell Is an Employer of Choice
• Cutting-edge networking silicon: Work on switch ASICs that define the next era of data center scale-out, cloud fabrics, and AI cluster interconnect.
• Impact at industry scale: The architectures you design will be deployed across hyperscale data centers globally.
• Technical leadership environment: Marvell empowers senior engineers to think big, drive cross-functional alignment, and influence long-term product direction.
• Collaborative on-site culture: Daily in-person collaboration accelerates innovation, strengthens technical rigor, and enables rapid iteration.
• Stability + growth: Marvell continues to expand in high-growth markets including AI, cloud, carrier networks, optical interconnects, and custom silicon.

What You Can Expect

As a Senior Principal Engineer, you will serve as a key technical leader driving architecture and execution for next-generation Teralynx switch products. You will:

• Define new features, pipelines, and protocols for next-generation data center switch chips.
• Deliver detailed behavioral and performance models to validate architectural decisions and ensure scalability for cloud-scale deployments.
• Drive end-to-end switch architecture from high-level concept through micro-architecture engagement and silicon bring-up.
• Partner with cross-functional engineering teams to ensure architectural intent is delivered through implementation and verification.
• Analyze tradeoffs across latency, throughput, memory architecture, power, area, and QoS to guide design decisions.
• Participate in customer-facing technical discussions, aligning product capabilities with real-world use cases and requirements.
• Contribute to long-term architectural direction and roadmap planning for the Teralynx product line.
• Mentor engineers, share best practices, and elevate architectural rigor across the organization.

What You Can Expect

• High ownership and visibility in defining and guiding major architectural features of Marvell’s flagship switch products.
• A deep, hands-on role in shaping silicon that scales to the next generation of cloud and AI data centers.
• A highly collaborative on-site engineering culture that accelerates problem solving and innovation.
• Opportunities to work across domains — hardware, software, systems, and customer engineering — broadening your technical influence.
• A stable environment with the resources of a global semiconductor leader, paired with the agility of a fast-moving product organization.
• A compensation and benefits package designed to attract top technical talent.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or related field and 15+ years of relevant experience, OR
• Master’s/PhD with 10–12+ years of experience in semiconductor architecture or ASIC development.
• Strong background designing or architecting complex ASICs, ideally in networking or switch domains.
• Deep knowledge of Layer 2 / Layer 3 forwarding, QoS, congestion management, and networking protocols.
• Expertise with behavioral and performance modeling, architectural validation, and system-level tradeoff analysis.
• Strong programming sk