Senior Applications Engineer (ASIC / PCIe IP Design)

General Information

Job Title Senior Applications Engineer (ASIC / PCIe IP Design) Job ID 4896 City Sunnyvale State/Province California Date Posted 03-Sep-2024 Job Category Engineering Job Subcategory Applications Engineering Hire Type Employee Remote Eligible No Base Salary Range: $173000 - $259000

Descriptions & Requirements

Job Description and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

PCIe Applications Engineer

This position requires a highly motivated and experienced person to work with Synopsys’ customers on integrating leading edge Interface IP (IIP) into their ASIC SoC/systems for next generation products.

The position offers opportunities to work on Synopsys PCIe (Peripheral Component Interconnect Express) IP and the latest industry specifications/applications on various hot market segments. The position will provide PCIe IP integration guidance to customers throughout their SoC flow to resolve technical challenges, perform integration reviews at key milestones and support silicon/system bring-up. Some travels will be required.

Responsibilities Include

• Understand about IIP applications on customer specific SoC and systems
• Keep abreast of the latest ASIC/SoC design flows and EDA tools