Silicon Design-for-Test (DFT) Engineer

<p><strong>What MatX Is Building</strong></p> <p>MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking a Silicon Design-For-Test (DFT) engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies in leading-edge process nodes.</p> <p><strong>What You'll Do Here</strong></p> <ul> <li>Design and develop functional test solutions for <strong>SERDES PHY</strong>, covering loopback, eye diagram characterization, and margin testing.</li> <li>Perform <strong>DFT integration</strong> of PHY IP blocks, including boundary scan, BIST interfaces, and test mode control signals, and develop robust pattern porting flows from IP-level to SoC-level.</li> <li>Develop and maintain <strong>firmware loading flows</strong> for PHY bring-up and test — including SPI/JTAG-based firmware download, register initialization sequences, and debug support during test program development.</li> <li>Collaborate closely with verification, firmware, and test engineering teams to develop and bring up silicon test programs from simulation to ATE.</li> <li>Execute DFT implementation and verification flows for <strong>block-level DFT insertion</strong>, including scan chain closure, ATPG pattern generation, and sign-off.</li> <li>Support test escapes root cause analysis and drive continuous improvement of DFT coverage and test quality.</li> </ul> <p><strong>Who You Are</strong></p> <ul> <li>Hands-on experience with <strong>DFT implementation</strong> — MBIST, at-speed scan and scan compression.</li> <li>Strong knowledge of modern DFT standards and protocols: <strong>JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN)</strong>.</li> <li>Experience or Working Knowledge of loading and validating <strong>PHY firmware</strong> via serial interfaces (SPI, I2C, or JTAG), including understanding of bootloader sequences and register map initialization.</li> <li>Solid experience integrating <strong>PHY DFT interfaces</strong> (e.g., SERDES PHY test modes, analog test buses into the SoC DFT architecture.</li> <li>Experience with <strong>system-level DFT access</strong> — hierarchical test access, test data compression, and multi-die/chiplet DFT — is a strong plus.</li>