CAD/EDA – Silicon Design/Verification Infrastructure

Job Description

Role: CAD/EDA – Silicon Design/Verification Infrastructure

Location: San Francisco, CA / Seattle, WA / Santa Clara, CA

Job Type: Contract

Interview: Phone/Skype

We are hiring a CAD/EDA Engineer with 5+ years of experience in EDA/CAD SoC/IP design or verification infrastructure development. Key skills include #Python (3.x), System Verilog/UVM, Linux scripting, and expertise in SoC design/verification flows. Responsibilities involve integration testing, design verification, and collaborating with cross-functional teams to drive quality and innovation.

#CAD  #EDA #Python #SystemVerilog #UVM #SoC #Verification #C2CHiring #Python

Additional Information

All your information will be kept confidential according to EEO guidelines.