Principal Engineer, CPU Micro-architecture

Please Note:

To provide the best candidate experience with our high application volumes, we limit applications to a total of 10 over 6 months. 

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We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

What You’ll Do

The APL (Advanced Processor Lab) is one of the research teams of SAIT (Samsung Advanced Institute of Technology) which is Samsung‘s R&D hub, established as the incubator for cutting-edge technologies. SAIT’s mission has covered various research areas from AI applications/algorithms research, neuromorphic processor, domain-specific accelerators to new materials, quantum computing, and super computer system.

APL is committed to shaping the future of CPU processor and SoC architecture for the most demanding applications of the future like AI and HPC. We are building the foundation of processors and the related platform which are applied to various business targets of Samsung in the future. 

We are seeking an experienced CPU Micro architect to join our high-performance CPU design team. In this role, you will be responsible for defining, developing, and optimizing the microarchitecture of cutting-edge CPU cores. You will work on everything from high-level design and microarchitectural specification to detailed RTL implementation and performance analysis.

Location: Hybrid, working onsite at our San Jose office 3 days per week, with the flexibility to work remotely the remainder of your time

Job ID: 42312

• Define and develop the microarchitecture for high-performance CPU/GPU/DSP/AI Engine cores for HPC, Datacenter or AI platforms/applications.
• Collaborate with team members to transform high-level CPU architectural models into detailed microarchitectural implementations.
• Optimize CPU designs for performance, power, and area while maintaining overall system coherence and efficiency.
•  Lead and participate in the design of key CPU components, including instruction pipelines, branch prediction, execution units, and memory subsystems.
•  Work closely with RTL engineers to ensure proper translation of microarchitecture specifications into clean and efficient RTL code.
•  Perform microarchitecture modeling and simulations to evaluate performance and ensure design robustness.
• Identify, debug, and resolve architectural and microarchitectural bottlenecks.
• Collaborate with verification, backend, and physical design engineers to ensure design goals are met across different domains.
•  Contribute to the CPU roadmap by identifying new techniques, features, and optimizations to stay ahead of industry trends.

.What You Bring

• Bachelors in Electrical/Computer Engineer with 20 years of relevant industry experience, or Masters in Electrical/Computer Engineer with 18 years or PhD in Electrical/Computer Engineer with 15 years preferred.
• 5+ years of experience in CPU design and microarchitecture, with hands-on experience in developing and optimizing microarchitectures for high-performance CPU cores.
• Strong understanding of CPU architectures, instruction sets (such as x86, ARM, RISC-V), and microarchitecture design principles (out-of-order execution, multi-level caches, branch prediction, etc.).
• Proficiency in RTL design, including experience with Verilog/System Verilog.
• Proven experience in microarchitecture modeling, simulation, and performance evaluation.
• Deep knowledge of pipelining, superscalar execution, and out-of-order execution architectures.
• Familiarity with memory hierarchies, including caches, TLBs, and memory management, cache coherence protocols etc.
• Experience with power and performance trade-offs. 

Preferred Skills:

• Experience with RISC-V/ARM/x86 architecture and other open-source CPU architectures.
• Knowledge of high-performance microarchitecture design techniques.
•  Proficiency in using performance tools and simulators such as gem5 or custom architectural models.
• Familiarity with multicore and multi-threaded CPU designs.
•  Understanding of ASIC physical design flows, including clocking, timing closure, and