Sr. Silicon Learning Lead

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Senior Silicon Learning Lead, you will help maximize PPA for Samsung’s premium mobile GPU by driving SARC/ACL’s focus on silicon learning. This is a vital role with high cross-functional visibility across the Samsung Semiconductor business. Your technical leadership on silicon learning will be key to bridge the power/performance gaps between silicon and design, and continually improve our physical design and signoff methodologies.

We believe in connecting your area of expertise with the right job level that can empower you to grow. This position may start at a higher level depending on your knowledge and experience. As a key leader in our Design Implementation organization, your solid background in silicon, physical design implementation, and technical leadership are desired for success.

• You thrive on driving collaboration with various stakeholders across the company to create working synergy between our R&D lab and the Foundry. You build a strong partnership with our partners in Korea on comprehending key product-level test data that captures GPU power and frequency along with silicon process parametrics.
• You are a domain expert in one or more technical areas. You can analyze silicon test data to correlate metrics such as operating frequency, Vmin, and power with respect to STA and power signoff flows.
• You are skilled at identifying areas of miscorrelation and partnering with other teams to define additional diagnostic collateral such as functional, scan, and memory test patterns.
• You enjoy working with the SARC functional debug and enablement team on focused board-level lab experiments to further diagnose areas of miscorrelation. This includes using special test modes to isolate silicon critical paths.
• You are passionate about problem solving. Your curiosity helps you identify the root-cause and crisply communicate specific reasons for the miscorrelation, along with helping define future improvements in design signoff and implementation.
• You have an innovative mindset. You will partner with DFT, RTL, and architecture teams to continually define new test features which will help us to diagnose and improve our silicon correlation for future designs.
• You are open-minded with an inclusive working manner to both individuals and groups of people that have diverse styles, abilities, and motivation. You will partner with our teams in Korea as needed on silicon diagnostic techniques such as LADA, transistor nanoprobing, and physical analysis.
• You have an ambition to master your technical craft through continuous learning and working on cutting-edge technology in a dynamic fast-paced global environment.

Skills and Qualifications

• 10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a PhD
• 10+ years of experience on physical design/signoff with industry-standard tools like Synopsys Fusion Compiler or Cadence Innovus.
• Strong expertise in one or more of the following areas:
  • Static Timing Analysis (STA): including tool/flow aspects with a deep understanding of timing-margining methodology, and non-ideal behaviors causing miscorrelation between silicon and design.
  • Dynamic voltage drop analysis and implications on silicon performance
  • Parametric silicon Vmin/fmax debug and silicon critical path isolation
• Working knowledge in areas such as circuit/memory design and DFT.
• Strong leadership ability with effective influencing skills to advocate for silicon learning and drive other stakeholders to achieve desired outcomes in a timely manner.
• Demonstrated technical problem-solving ability with a self-starter mindset.
• Effective technical mentorship skills
• Effective communications (verbal and written) and interpersonal skills to work with diverse global stakeholders
• Adaptability skills to manage competing priorities in a fast-paced environment (i.e. yearly new product introductions on leading edge process nodes)

Our Team

We’re strengthening our team of talented individuals with diverse skill sets to build a technology roadmap and deliver market-leading GPU. Our Xclipse GPU is the first mobile G