SerDes Analog / System Design Architect

General Information

Job Title SerDes Analog / System Design Architect Job ID 7180 City US (non-CA) Off-Site State/Province US (non-CA) Off-Site Office Date Posted 28-Oct-2024 Job Category Engineering Job Subcategory Analog Design Hire Type Employee Remote Eligible Yes Base Salary Range: $174000 - $262000

Descriptions & Requirements

Job Description and Requirements

System Level Architect 

 

You will be part of an R&D team developing >100Gbps NRZ and PAM4 serial-link transceivers as part of our Enterprise Serdes team for PCIe and Ethernet protocols. We are looking for an engineer with theoretical knowledge and practical experience to contribute and to lead the team. You will work with a cross functional design team of analog and digital designers, and hardware engineers.
 
You will be involved in all stages of development including:

• Architecture: definition of architecture and specifications for the transmitter and receiver
• Modelling:   design and maintenance of the system level model
• Signal/Power Integrity: analyzing different signal and power integrity requirements  
• Sign-off: system level simulation of the design performance across multiple protocols and channels
• Silicon: qualification and correlation of performance and algorithms in silicon
• Customers:  assisting customers on system level performance and algorithmic issues 

 

You have a MSc or PhD in Electrical or Computer Engineering.

 

Due to the cross disciplinary nature of this position, key qualifications include one or more of the following…

• Modelling - experience in Matlab/Simulink/C modeling of circuits and systems
• Communications theory – e