Lead Advanced Microelectronics Packaging Design Engineer

Lead Advanced Microelectronics Packaging Design Engineer

Company:

The Boeing Company

Boeing Defense Space & Security has an exciting opportunity as a Lead Advanced Microelectronics Packaging Design Engineer. Come join us as part of our Electronics Packaging team located in El Segundo, CA.

Packaging Electronics team focuses the majority of their time on Satellite missions. However, our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line – approximately half our design work is within the Space & Launch business unit, and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems)..

Using first principals thinking, Engineers will work on electronic packaging designs and take it from cradle to grave. Working within a collaborative team environment, surrounded by world class engineers and mentors, you will design within the full life cycle and see your work from proposal all the way to delivery and production. We’re highly supportive of innovative thinking, we respect and acknowledge hard work, we recognize maturity and integrity, and we reward bottom-line achievement.  At Boeing, we value your curiosity, your determination, and your imagination. #YouWillChangeTheWorld

Position Responsibilities:

• Designing and optimizing layout for advanced substrates of HDI IC substrate, Silicon, or LTCC substrates, considering electrical, thermal, and mechanical requirements.

• Collaborate in multi-functional discussions for package architecture and technology roadmap (partner with Silicon IC team to optimize chip Floorplan and bump placement).

• Cross-functional interface with IC design, materials, SI/PI, thermal, systems, and production teams to optimize package solutions on cost, performance, manufacturability, and reliability

• Interface with packaging assembly and substrate suppliers for new product bring-up, qualification and production ramp

• Interface with other operations functional groups such as product engineering, foundry, test, and QA

• Create and execute substrate breakout patterns for ASIC packaging

• Optimize package pinouts by evaluating system-level trade-offs - Conduct package routing, placement, stack-up, reference plane, and power distribution activities

• Conduct design feasibility studies to assess package design goals encompassing size, cost, and performance

• Develop symbols and CAD library databases using Cadence APD or Mentor Xpedition tools

• Works under minimal direction

Basic Qualifications (Required Skills/Experience):

• Ability to obtain a U.S. Security Clearance

• Bachelor of Science degree from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), chemistry, physics, mathematics, data science, or computer science

• 5 years of experience as a substrate designer or 9+ years of professional experience with substrate layout design

• Hands-on experience with package design and proficient in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP) or Mentor Xpedition platform tools.

Preferred Qualifications (Desired Skills/Experience):

• Experience with TSV, 2D/2.5D and 3D package connection.

• Hands-on expertise of advanced and new assembly processes for flipchip, wirebond, and MCM packages

• SI/PI tools (XtractIM, PowerSI, HFSS, Q3D, etc.), package model extraction, S-parameters and RLGC model.

• Substrate manufacturing process, structure, design rules and material property.

• Solid understanding of high-speed interfaces, including DDR, PCIe, NAND, etc.

• Consistent track record to drive package selection through feasibility studies and drive chip Floor planning and bump assignment.

• Familiar with package design reviews and familiarity with CAM350/Valor or Calibre and CAD.

• Knowledge of high-speed layout constraints (crosstalk mitigation, differential pairs, EMI/RFI, PCB/package resonance).

• Familiar with Cadence Concept HDL for schematic review, experience in schematic capture and system integration.

• Experience in advanced node