Senior Manager, Silicon Product and Test Engineering

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience in IC product development or test engineering, and manufacturing (i.e., characterization, qualification, bring-up, yield improvement, and debug).
• 6 years of experience in people management, developing employees.
  
• Experience building test program and HVM floor engineering support/management.
• Experience working with vendors.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience in wafer probe card, ATE hardware, and managing suppliers on execution of test hardware development and bring-up.
• Experience in test engineering, DFT, test hardware, and test program development (e.g., Teradyne UltraFlex, Advantest 93k platforms).
• Experience in programming/scripting (e.g., C and C++, Python, or Perl).
• Knowledge of probability and statistical fundamentals for data analysis and process control design.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Technical Lead Manager, you will build high quality manufacturing flow and take it to HVM (High Volume Manufacturing). You will define, lead, and track our products operation covering HVM, NPI, ATE Test and Characterization, System level Testing, Burn In, Cost reduction and Yield improvements processes. You will deliver products in the fabless semiconductor model with knowledge covering the full manufacturing flow, including high-volume production, fab, test, DFT, package assembly, and qualification.

In this role, you will be managing a team that is responsible for developing test programs and hardware for wafer probe and the ATE (Automated Testing Equipment) for characterization and production testing of very high performance networking and machine learning ICs. You will be able to utilize the ATE equipment tools and capabilities to optimize final test programs without compromising the quality of outgoing products. You will also be responsible for developing test plans and supporting the full life cycle of the product from design to volume manufacturing till end of life.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $227,000-$320,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead Post Silicon Engineering Activities from DFT requirements, including New Product Introduction (NPI), System Level testing, and HVM (including Yields analysis and Return Merchandise Authorization (RMA)/Failure Analysis (FA).
• Lead a team to develop silicon product test hardware and software, silicon data analytics, and system level testing.
• Work closely with