Sr. Engineer, RTL Implementation

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>We are looking for a talented engineer to join our CPU design team to iterate through front-end CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design.</p> <p>This role is<strong>&nbsp;</strong>hybrid, based out of Austin, TX or Santa Clara, CA.</p> <p>We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p> <p>&nbsp;</p> <p><strong>Who You Are</strong></p> <ul> <li>Experienced in high-performance physical design.</li> <li>Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis.</li> <li>Skilled in synthesis, place and route tools including flows and physical design methodology.</li> <li>Background in CPU micro-architecture.</li> </ul> <p>&nbsp;</p> <p><strong>What We Need</strong></p> <ul> <li>Perform synthesis and initial place and route for new and legacy designs.</li> <li>Collaborate closely with core micro-architects to optimize core configurations for best PPA.</li> <li>Use innovative techniques to optimize power, performance, and area while driving physical design experiments and evaluating results.</li> <li>Enhance physical design environment, tools, and methodologies to improve development efficiency.</li> </ul> <p>&nbsp;</p> <p><strong>What You Will Learn</strong></p> <ul> <li>End-to-end exposure to CPU design from microarchitecture through timing and power convergence.</li> <li>Hands-on experience optimizing CPU designs and driving PPA improvement.</li> <li>Integration of open-source and industry-standard tools to improve physical flows an