Senior Quantum Analog Layout Engineer
MicrosoftAbout the role
Microsoft's Quantum team is building the first scalable, fault-tolerant quantum computer, advancing everything from quantum hardware and error correction to Azure integration. Our full-stack strategy spans the physics of quantum devices through scalable readout and control infrastructures powered by cryo-electronics. As quantum computing enters a pivotal phase of accelerated growth, this position offers a unique opportunity to contribute meaningfully to a transformative technology, such as the Application Specific Integrated Circuits (ASICs) and analog circuitry developed by this team.
As a Senior Quantum Analog Layout Engineer on the Quantum 1st Party Hardware ASIC team, you will play a critical leadership role in advancing Microsoft's quantum analog infrastructure, driving Analog Layout designs and coordinating employees, contingent staff, and external vendors to deliver high-quality designs.
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
- Deliver Schematic-to-Graphic Database System (GDS) layouts for cutting-edge, high-performance, high-speed, low-power IP designs, including interconnectivity solutions and foundational Analog circuit blocks. Execute these layouts across multiple process nodes, including deep Fin Field-Effect Transistor (FinFET), following industry best practices.
- Develop plans for Analog Mask Layout execution and follow processes and methodologies to deliver IP blocks. Coordinate tasks with junior layout team members as needed.
- Using Cadence Virtuoso (or other equivalent) design tools and flows; perform layout implementation of analog-intensive IPs and help establish flows, methodologies, and processes for execution alongside peers.
- Support the on-boarding and off-boarding of contingent layout staff and vendor partners as needed; help direct their day-to-day execution to ensure quality and schedule are met.
- Work with other members of the team to deliver IPs, including project planning, schedule tracking, and report generation. Follow, augment, or put in place processes and methodologies for high-quality execution alongside peers.
- Other
Qualifications
Required/minimum qualifications
- Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
- OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
- OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
- OR equivalent experience.
Other Requirements
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
- Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administr
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