Principal Digital Verification Engineer

Job Title:                 Principal Digital Verification Engineer 

Job Duties:              Develop battery management IC’s for automotive applications. Take charge of the UVM and System Verilog based Digital Verification flow, ensuring the IC functions correctly as intended. Establish and implement verification standards, metrics and policies. Develop and integrate                                     the testing environment and automation scripting to run the testing procedures and operations. Responsible for UVM and System Verilog based Digital Verification environment definition and development for power management ICs.; also in charge of VIPs standardization,                                                 definition, development and documentation, and Digital Verification Metrics definition for RTL and Gate-Level Verification; defining VIP integration into Project’s Digital Verification environment, Automation, and Scripting. 

Job Requirements:  Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or VLSI Design, plus three years of experience in the offered position or as a Design Automation Engineer, Pre-Silicon Verification Engineer, Verification Engineer, Member of Technical Staff 

Salary:                     $ 189,257.90.per year

Job Site:                     Job Site:                  Chandler, AZ