Senior Engineer, Design Verification

<p><b><span>About Analog Devices</span></b></p><p><span>Analog Devices, Inc. (NASDAQ:<span> </span></span><u><span><a href="http://finance.yahoo.com/q?s=ADI" rel="noopener noreferrer" target="_blank"><span>ADI</span></a></span></u><span> ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at<span> </span></span><u><span><a href="https://www.analog.com/" rel="noopener noreferrer" target="_blank"><span>www.analog.com</span></a></span></u><span> and on<span> </span></span><u><span><a href="https://www.linkedin.com/company/analog-devices/posts/?feedView=all" rel="noopener noreferrer" target="_blank"><span>LinkedIn</span></a></span></u><span> and<span> </span></span><u><span><a href="https://x.com/adi_news" rel="noopener noreferrer" target="_blank"><span>Twitter (X)</span></a></span></u><span>.</span></p><p>          </p><p><span> </span></p><p><span><span>The charter of ADI’s CSS team is to lead the market in selected technology domains with highly differentiated sensing and signal processing solutions. Today these </span><span>technology</span><span> areas include Capacitive Sensing, Optical Image Stabilization</span><span>, Power management</span><span> and Audio that drive growth in our portable and non-portable consumer business. </span><span>As part of our global operation and expanding business needs, we are now seeking to fill key roles in defining, developing</span><span> and implementing verification solutions </span><span>for</span><span> mixed signal ICs in</span><span> this key market area. This would s</span><span>p</span><span>an the entire development cycle from concept phase, through </span><span>verification </span><span>planning</span><span>,  implementation</span><span>, execution</span><span>, and release of products to </span><span>customers. The</span><span> Design Verification Engineer will collaborate with the wider</span></span><span><span> ADI technical community which affords an </span></span><span><span>opportunity to work with many business units in ADI with exposure to many technologies and products</span></span><span> </span></p><p><b><span>Responsibilities</span></b><span> </span></p><p><span> </span></p><p><span><span>Based </span><span>in</span><span> Edinburgh </span></span><span><span>this position will be responsible for</span><span> contributing to</span><span>:</span></span><span> </span></p><ul><li><p><span><span>Verification of complex designs and sub-systems using leading edge verification methodologies</span></span><span> </span></p></li></ul><ul><li><p><span><span>Contribute</span><span> to</span><span> and </span><span>Influence</span><span> the decisions on methodologies</span><span>/strategies</span><span> to be adopted for </span><span>design </span><span>verification.</span><span> </span></span><span> </span></p></li></ul><ul><li><p><span><span>Develop </span><span>testbench </span><span>architectures</span><span> </span><span>and develop </span><span>using</span><span> UVM or Formal based verification approaches. </span></span><span> </span></p></li></ul><ul><li><p><span><span>Define </span><span>verification</span><span>-</span><span>plan</span><span>s</span><span>, </span><span>functional coverage, </span><span>tests and verification methodology for block/chip-level verification. Work with the design team in generating </span><span>verification</span><span>-plans and closure </span><span>metrics</span><span>.</span></span><span> </span></p></li></ul><ul><li><p><span><span>Debugging of</span><span> Gate Level Simulation (GLS)</span><span>, </span><span>waiving Timing Violations approved by designer</span></span><span> </span></p></li></ul><ul><li><p><span><span>Continuous interaction with analog co-sim and firmware team</span><span>.</span></span><span> </span></p></li></ul><ul><li><p><span><span>Technically mentor and guide junior verification engineers on SoC Verification.</span></span><span> </span></p></li></ul><ul><li><p><span><span>Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team</span></span><span> </span></p></li></ul><ul><li><p><span><span>Lead verification effort</span><span>s at IP or SoC level, </span><span>effort estimation, project scheduling and tracking,</span><span> task </span><span>assignment, </span><span> reporting</span><span> to management </span><span>or customer.</span></span><span> </span></p></li></ul><p><span> </span></p><p><b><span>Qualifications</span></b><span> </span></p><p><span> </span></p>