Semiconductor Radiation Effects Engineer (Associate, Mid-Level or Lead)
BoeingAbout the role
Company:
The Boeing CompanyBoeing Research & Technology is current looking for a Semiconductor Radiation Effects Engineer (Associate, Mid-Level or Lead) to join the team based in Huntington Beach, CA
We are Boeing Research & Technology (BR&T): Boeing's global research and development team creating and implementing innovative technologies that make the impossible possible and enabling the future of aerospace. We are engineers and technicians, skilled scientists and bold innovators; Join us and put your passion, determination, and skill to work building the future! #TheFutureIsBuiltHere #ChangeTheWorld
Within BR&T, Boeing’s Solid State Electronics Development organization (SSED) performs microelectronics technology development and design for aerospace systems. We develop digital, analog, and RF Systems on Chip (SoCs) for radar, navigation, electronic warfare, communications, processing, and other electronic systems. These systems are used on Boeing airborne, terrestrial, and satellite platforms. SSED has numerous microelectronics projects, funded both by internal Boeing customers and external Government Science and Technology (S&T) customers, and is nationally recognized in aerospace microelectronics design communities.
SSED executes a variety of exciting, technically challenging projects, offering endless opportunities to develop depth and breadth of technical skills. We offer on-the-job learning opportunities and long-term potential for career growth into both technical leadership and/or management positions and seek curiosity, creativity, innovation, attention to detail, clear communication, and the ability to understand and meet customer needs.
Semiconductor radiation effects engineers will conduct radiation test, analysis, and modeling of integrated CMOS circuits. They will define the future of radiation effects characterization and mitigation by developing novel test, analysis, modeling, and mitigation techniques and approaches.
Position Responsibilities:
Analyze, model, and predict radiation effects in semiconductor devices and integrated circuits
Lead or execute Total Ionizing Dose (TID), Single Event Effects (SEE), prompt dose, and displacement damage radiation test campaigns
Perform analysis of radiation test data, including rate estimates
Prepare test plans and test reports
Develop and validate design and/or architectural radiation mitigation techniques, working with design team
Present to program management, leadership, and customers
This position is expected to be 100% onsite. The selected candidate will be required to work onsite at one of the listed location options.
This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret clearance Post-Start is required.
Basic Qualifications (Required Skills/Experience):
Bachelor of Science degree from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), chemistry, physics, mathematics, data science, or computer science
1+ years of experience in semiconductor radiation effects
Preferred Qualifications (Desired Skills/Experience):
3+ years of related work experience or an equivalent combination of education and experience
5+ years of related work experience or an equivalent combination of education and experience
Experience conducting TID, SEE, prompt dose, and displacement damage testing on advanced analog, digital, and mixed signal ICs
Experience modeling TID, SEE, prompt dose, and neutron effects in semiconductor devices and ICs
Experience with advanced commercial semiconductor fabrication process technologies, including multi-gate (e.g. FinFET), silicon-on-insulator (SOI), and silicon germanium (SiGe) processes
Experience with experimental process technologies (e.g. Gate-all-around FETs (GAAFETs))
Experience with design and test of electronics for extreme environments
A clear understanding of IC design flow from device-level modelling through library development and final chip-level design and verification.
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